1. Field of the Invention
The present invention relates to an integrated circuit, and more particularly, to a converter for converting into a digital signal the difference between the times at which two signals are input and a locking circuit and method for generating a periodic signal such as a clock signal using the converter.
2. Description of the Related Art
Integrated circuits which operate at high speed require locking circuits for generating periodic signals which have a synchronous relationship with reference clock signals. In particular, semiconductor products such as synchronous dynamic random access memories (SDRAM) require locking circuits.
A locking circuit in a SDRAM generates internal clock signals which are synchronized with reference clock signals. The SDRAM drives its internal circuits, which are related to the input of data and the input/output of commands, based on the internal clock signals. Generally, a locking circuit generates an internal clock signal having the same phase as that of a reference clock signal, using a feedback circuit. An internal circuit using the internal clock signal generated by the locking circuit may be physically located at a different position to the locking circuit in a memory chip. Accordingly, a skew, in which an internal clock signal actually used in an internal circuit does not have the same phase as that of a feedback signal that is controlled by a feedback circuit, may occur. The skew causes the phase difference between an internal clock signal which is actually used in an internal circuit and a reference clock signal.
Designers of locking circuits have tried to minimize the phase difference between an internal clock signal actually used in an internal circuit and a reference clock signal. A representative locking circuit is a delay locked loop.
As shown in FIG. 1, in a conventional delay locked loop, a phase detector 105 compares a reference clock signal ECLK with a feedback signal FCLK1. The phase detector 105 provides a phase difference signal DET to a delay unit 101. The phase difference signal DET corresponds to the phase difference between the reference clock signal ECLK and the feedback signal FCLK1 and is controlled over its activation width. The delay time of the delay unit 101 is controlled by the activation width of the phase difference signal DET. A clock driver 103 is driven by a delay clock signal DCLK output from the delay unit 101 and generates an internal clock signal ICLK. A mirror delay circuit 107 reflects path delay from an output terminal of the clock driver 103 to the point at which the internal clock signal ICLK is actually used. In other words, the mirror delay circuit 107 delays an auxiliary clock signal FCLK0, which has an identical phase to that of the internal clock signal ICLK at the output terminal of the clock driver 103, by the path delay of the internal clock signal ICLK to generate a feedback signal FCLK1.
The delay time of the mirror delay circuit 107 may be changed by fabrication conditions, temperature and the value of the power supply voltage. A change of the delay time causes the phase difference between a feedback signal and an internal clock signal that is actually used in an internal circuit. In addition, the mirror delay circuit in a conventional delay locked loop has a fixed delay time. Accordingly, the phase difference between a feedback signal and an internal clock signal cannot be controlled. Consequently, there is a problem in that the phase difference between a feedback signal and an internal clock signal causes the phase difference between an internal clock signal which is provided by a conventional delay locked loop and a reference clock signal.
To solve the above problems, it is an object of the present invention to provide an integrated circuit having a locking circuit for minimizing the phase difference between a reference clock signal and an internal clock signal.
It is another object of the present invention to provide a locking method for minimizing the phase difference between a reference clock signal and an internal clock signal using the locking circuit.
In one aspect, the present invention provides an integrated circuit having a locking circuit for generating an internal clock signal in synchronization with an input reference clock signal. The internal clock signal is obtained when an initial internal clock signal at an output terminal of the locking circuit is delayed by a predetermined time for which the initial internal clock signal is transmitted from the output terminal to an input terminal of a circuit at a predetermined distance from the output terminal. The locking circuit includes an internal clock signal generator for delaying the reference clock signal by a first delay time corresponding to the phase difference between the reference clock signal and a feedback signal which is controlled to have the same phase as that of the internal clock signal. The internal clock signal generator generates the initial internal clock signal based on the delayed reference clock signal. A mirror delay circuit delays the initial internal clock signal by a second delay time in response to a predetermined delay control signal group and generates the feedback signal. A time-to-digital converter generates the delay control signal group for controlling the mirror delay circuit to reduce the phase difference between the feedback signal and the internal clock signal.
In another aspect, the present invention provides an integrated circuit having a locking circuit for generating an internal clock signal in synchronization with an input reference clock signal. The internal clock signal is obtained when an initial internal clock signal at an output terminal of the locking circuit is delayed by a predetermined time for which the initial internal clock signal is transmitted from the output terminal to an input terminal of a circuit at a predetermined distance from the output terminal. The locking circuit includes an internal clock signal generator for delaying the reference clock signal by a first delay time corresponding to the phase difference between the reference clock signal and a feedback signal which is controlled to have the same phase as that of the internal clock signal. The internal clock signal generator generates the initial internal clock signal and an auxiliary clock signal based on the delayed reference clock signal. A mirror delay circuit delays the auxiliary clock signal by a second delay time in response to a predetermined delay control signal group and generates the feedback signal. A time-to-digital converter generates the delay control signal group for controlling the mirror delay circuit to reduce the phase difference between the feedback signal and the internal clock signal.
In still another aspect, the present invention provides an integrated circuit having a locking circuit for generating an internal clock signal in synchronization with an input reference clock signal. The internal clock signal is obtained when an initial internal clock signal at an output terminal of the locking circuit is delayed by a predetermined time for which the initial internal clock signal is transmitted from the output terminal to an input terminal of a circuit at a predetermined distance from the output terminal. The locking circuit includes an internal clock signal generator for delaying the reference clock signal by a first delay time corresponding to the phase difference between the reference clock signal and a feedback signal which is controlled to have the same phase as that of the internal clock signal. The internal clock signal generator generates a pre-clock signal and the feedback signal based on the delayed reference clock signal. A variable delay circuit delays the pre-clock signal by a second delay time in response to a predetermined delay control signal group and generates the initial internal clock signal. A time-to-digital converter generates the delay control signal group for controlling the variable delay circuit to reduce the phase difference between the feedback signal and the internal clock signal.
In yet another aspect of the present invention, there is provided a locking method for generating an internal clock signal which is synchronized with an input reference clock signal. In accordance with the locking method, the reference clock signal is delayed by a first delay time corresponding to the phase difference between the reference clock signal and a feedback signal which is controlled to have the same phase as that of the internal clock signal. An initial internal clock signal and an auxiliary clock signal are generated based on the delayed reference clock signal. The auxiliary clock signal is delayed by a second delay time, and the feedback signal is generated. The phase difference between the internal clock signal and the feedback signal is detected, and the phase difference between the internal clock signal and the feedback signal is converted into a digital signal. A predetermined delay control signal group based on the digital signal is generated, and the second delay time is controlled according to the delay control signal group to reduce the phase difference between the feedback signal and the internal clock signal.
According to the integrated circuit having a locking circuit of the present invention, the phase difference between two input signals is readily converted into a digital signal. Moreover, according to the locking circuit and method of the invention, the phase difference between a feedback signal and an internal clock signal is quickly reduced within a short time.